Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

TL;DR

A developer has demonstrated a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 platform. This marks a significant step in porting the system to modern open architectures, with implications for education and research.

A developer has shared a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 platform. This development, posted on Show HN, demonstrates the feasibility of porting Oberon to modern open-source architectures, with potential implications for education, research, and hardware experimentation.

The project was presented by an individual developer who has successfully ported the Oberon System—originally designed for the RISC-5 architecture—to run on RISC-V hardware. The port has been shared publicly via the Show HN platform, with the developer providing a working version and some documentation. The port aims to preserve the core features of Oberon, including its minimalistic design, integrated development environment, and hardware management capabilities.

According to the developer, this port allows Oberon to operate on open-source RISC-V processors, opening possibilities for educational use and hardware experimentation outside proprietary systems. The project is still in early stages, with some features yet to be fully tested or stabilized, but the core system is reportedly functional on RISC-V boards.

At a glance
updateWhen: announced recently, ongoing development
The developmentA Show HN post reveals a Project Oberon system ported from RISC-5 to RISC-V architecture, showcasing the OS running on new hardware.

Implications for Open-Source Hardware and Education

This port represents a significant step in making the Oberon operating system accessible on modern open-source hardware. It could enable educational institutions and researchers to experiment with a lightweight, self-contained OS directly on RISC-V processors, which are gaining popularity in academia and industry. Additionally, it demonstrates the flexibility of Oberon’s design, which was originally created in the 1980s, to be adapted to contemporary architectures, potentially inspiring further development and customization.

While the project is still in early stages, its success could influence the adoption of Oberon in new contexts, especially in environments emphasizing open hardware and software freedom. The port may also serve as a proof of concept for other legacy or niche operating systems considering modernization efforts.

XIAO ESP32C3 3PCS Pack - RISC-V Tiny MCU Board with Wi-Fi and Bluetooth5.0, Battery Charge Supported, Power Efficiency and Rich Interface

XIAO ESP32C3 3PCS Pack – RISC-V Tiny MCU Board with Wi-Fi and Bluetooth5.0, Battery Charge Supported, Power Efficiency and Rich Interface

  • MCU Chip: ESP32-C3 RISC-V 32-bit, up to 160MHz
  • Development Ports: Multiple interfaces for flexibility
  • Compatibility: Supports Arduino, MicroPython, PlatformIO, and more

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As an affiliate, we earn on qualifying purchases.

Background of Project Oberon and RISC-V Compatibility Efforts

Project Oberon was originally developed by Niklaus Wirth and colleagues at ETH Zurich in the 1980s as both an operating system and programming language environment. It is known for its simple, minimalistic design and tight integration of hardware and software components. Historically, Oberon ran exclusively on specialized hardware, notably the RISC-5 architecture, which was designed for academic purposes.

In recent years, the RISC-V architecture has gained widespread interest as an open-source, royalty-free alternative to proprietary processor designs. Many projects have aimed to port existing operating systems to RISC-V, but comprehensive efforts to adapt legacy systems like Oberon have been limited. This recent development marks one of the first known successful portings of Oberon to RISC-V, as shared publicly on Show HN.

Prior attempts to run Oberon on other hardware platforms have been mostly experimental or limited to emulators, making this port notable for its real hardware implementation and community visibility.

“This project demonstrates that Oberon can be adapted to modern open hardware, opening new avenues for education and research.”

— the developer behind the port

RISC-V FOR EMBEDDED SYSTEMS: THE COMPLETE DEVELOPMENT GUIDE: Build IoT, Automotive, Edge Devices with Open-Source Processors. Microcontrollers, Real-Time OS, AI Acceleration and Production Deployment

RISC-V FOR EMBEDDED SYSTEMS: THE COMPLETE DEVELOPMENT GUIDE: Build IoT, Automotive, Edge Devices with Open-Source Processors. Microcontrollers, Real-Time OS, AI Acceleration and Production Deployment

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As an affiliate, we earn on qualifying purchases.

Extent of System Stability and Feature Completeness

It is not yet clear how fully stable or complete the port is. The developer has shared a working version, but some features or hardware support may still be experimental or incomplete. Further testing and community feedback are needed to assess the system’s robustness.

Project Oberon: The Design of an Operating System and Compiler (Acm Press Books)

Project Oberon: The Design of an Operating System and Compiler (Acm Press Books)

As an affiliate, we earn on qualifying purchases.

As an affiliate, we earn on qualifying purchases.

Next Steps for Development and Community Engagement

The developer plans to continue refining the port, potentially adding more hardware support and improving stability. They also intend to share detailed documentation and encourage community testing and development. Monitoring the project’s progress will reveal how widely it is adopted and whether it influences broader porting efforts of legacy OSes to RISC-V.

Waveshare ESP32-C5 Mini Development Board, Equipped with 32-bit RISC-V Processor, Integrated 2.4GHz/5GHz Dual-Band Wi-Fi 6 and BLE 5

Waveshare ESP32-C5 Mini Development Board, Equipped with 32-bit RISC-V Processor, Integrated 2.4GHz/5GHz Dual-Band Wi-Fi 6 and BLE 5

  • Processor: 32-bit RISC-V up to 240MHz
  • Memory: 384KB SRAM, 320KB ROM, 4MB Flash
  • Wi-Fi Bands: Dual-band 2.4GHz/5GHz Wi-Fi 6

As an affiliate, we earn on qualifying purchases.

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Key Questions

What is Project Oberon?

Project Oberon is a minimalistic operating system and programming environment developed in the 1980s at ETH Zurich, known for its simplicity and integration of hardware and software.

Why is porting Oberon to RISC-V significant?

Porting Oberon to RISC-V makes the OS accessible on open-source, modern hardware, enabling new educational and research applications outside proprietary systems.

Is the port fully functional and stable?

The port is reportedly functional but still in early development stages. Some features or hardware support may be incomplete or experimental.

Who developed this port?

The port was created and shared by an individual developer on Show HN, with ongoing development and community engagement expected.

What are the implications for future OS ports?

This effort demonstrates that legacy systems like Oberon can be adapted to modern architectures, potentially encouraging similar projects for other operating systems.

Source: hn

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